Current sensing circuits typically are used in multiple applications, for example, voice coil motors, and in particular, in the current loop control devices for driving coils in these motors. These control devices comprise typically at least one current sensing circuit, also called a sense amplifier, which senses a current flowing through a suitable current-sense resistor associated with the coils of the motor. In these devices, and feedback drives the coils. Voice coil motors are used in high performance applications at high operating frequencies.
To reduce the power consumption in these applications, the coils of the motor may be driven by way of a current alternated switching from a linear standard mode to a pulse width modulation mode (PWM). In particular, the standard mode is used when the coils run currents with reduced amperage, switching to the PWM mode when currents with high amperage are run.
For example, in applications where the current reading is for memory storage support services, for example, in a hard disk drive, the current is modulated in the PWM mode during the so called track seek operations, switching to the linear standard mode during the track following operations.
A parameter that can limit the performance of the current loop control device, in applications with PWM currents, is common mode rejection ratio (CMRR). In fact, as is typical, a low CMRR introduces an additional signal in the current feedback depending on the voltage value of the input common mode and moreover, at the high operation frequencies, the CMRR parameter could reduce the phase margin of the passing band of the device itself, thereby jeopardizing its performance.
In particular, to avoid the influence of the output voltage of the current loop control device interfering or limiting the current in the coil of the motor, it is helpful for this output voltage to be independent from the common mode voltage at the input of the current sensing circuit. In these applications, the current loop control device and, in particular, the current sensing circuit, may show an input offset being as low as possible.
The current sensing circuit, in the typical approach, comprises standard differential amplifiers and structures of the Gm/Gm type. A typical scheme for a differential amplifier used in a current sensing circuit 10 for applications to voice coil motors is shown in FIG. 1. The sensing circuit 10 comprises, in particular, an operational amplifier OP and four resistors Ri i=1 . . . 4, which define a gain of the operational amplifier OP.
The operational amplifier OP is connected to a terminal, placed at a supply voltage Vcc, and a ground terminal Gnd, placed at the ground voltage, and has a first input terminal I1, in particular, inverting (−), connected to a first input terminal IN1 through a first resistance R1, a second input terminal I2, in particular non inverting (+), connected to a second input terminal IN2 through a second resistance R2, and an output terminal Out on which an output voltage signal is generated Vout. An input differential voltage Vdiff is applied to these first IN1 and second input terminals IN2.
The sensing circuit 10 comprises a third resistance R3 feedback connected between the output terminal Out and the first inverting input terminal I1 of the operational amplifier OP, as well as a fourth resistance R4 inserted between the second non-inverting input terminal I2 of the operational amplifier OP and a reference terminal TR receiving a reference voltage Vref.
Although advantageous, this approach for the current sensing circuit for applications of the above indicated type has some limits, in particular, to the CMRR parameter, which is influenced by the value of the resistances connected to the operational amplifier OP. In fact, considering the common mode voltage at the input terminals IN1 and IN2 has a similar value to the reference voltage Vref, the current that flows through the third feedback resistance R3 is low and thus the output voltage Vout, generated at the output terminal Out, remains almost equal to a value, in particular, the reference voltage value Vref.
However, by increasing the value of the input common mode voltage up to the value of supply voltage Vcc, for example, about 12V, a mismatch of the resistances R1-R4 occurs, a current flows in the third feedback resistance R3, and the output voltage Vout increases with respect to the reference voltage value Vref, thus determining an output signal Vout, although a differential input signal Vdiff equal to zero is present.
In the illustrated example of the sensing circuit 10, the worst value of the CMRR parameter due to the coupling of the resistances R1-R4, without considering any contribution of the operational amplifier OP, results from the formula:
  CMRR  =            K      +      1              4      ⁢      t      where: K is the total gain of the operational amplifier OP; and t is a realization tolerance or matching coefficient of the resistances R1-R4 in the sensing circuit 10.
A practical example of calculation of the coefficient t and thus of the value of CMRR is provided by the following formula:
  t  =                    11        ⁢        %                    WL              =                            11          ⁢          %                                      16            *            280                              =              0.165        ⁢        %        ⁢                                  ⁢        at        ⁢                                  ⁢        1        ⁢                  δ          ⁡                      (                          0.66              ⁢              %              ⁢                                                          ⁢              at              ⁢                                                          ⁢              4              ⁢              δ                        )                              where W and L indicate the sizes of an area occupied by the resistors.
For the sensing circuit 10, realized as shown in FIG. 1, the maximum value of CMRR is equal to:
  CMRR  =                    K        +        1                    4        ⁢        t              =                  3                  4          *          0.0066                    =              41        ⁢                                  ⁢        dB            It is to be noted that, according to this embodiment, by doubling the value of the area occupied by the resistors R1 and R3, the value of CMRR would take the maximum value of 44 dB against an area occupied by the circuit being, as a whole, excessively high. From this analysis, it is clear to a skilled person how the use of the resistances of the trimming type to reach at least a value of CMRR equal to 60 dB, with the configuration shown in FIG. 1.
FIGS. 3 and 4 show two diagrams obtained by so called Montecarlo analysis carried out on the sensing circuit 10 of FIG. 1, where the offset of this circuit is shown according to a first input voltage value equal to O V and to a second input voltage value equal to 13.2 V.
From a comparison of these diagrams one can evaluate how a mismatch of the resistances R1 and R3 can affect the value of the output voltage Vout. In particular, considering the relation:
      Output    ⁢                  ⁢    variation    =                              (                                    8.15              ⁢                                                          ⁢              mV                        -                          1.15              ⁢                                                          ⁢              mV                                )                *        Gain                    13.2        ⁢                                  ⁢        V              ⁢                  ⁢                  =                  1.06        ⁢                                  ⁢        m        *        4        ⁢        σ            ⁢                          ⁢                          =                        -          48                ⁢                                  ⁢        dB            and a differential gain of the circuit equal to two, the value can be calculated of the variation of the output voltage Vout in decibel (Output variation) and the corresponding value of CMRR:CMRR=−48 dB−[Gain(dB)]=−48 dB−20 Log 2=−54 dB.
FIG. 5 shows a diagram, which reports the progress of the reduction of the output voltage Vout of the sensing circuit 10 supplied by an alternated current and having a mismatch value of the resistances R1 and R3 equal to 0.65%, which represents the worst case. As it can be noted, after a transient, there is a reduction at the output equal to −48 dB and results confirm the variation value of the output voltage Vout previously calculated.
From this analysis, it can be deducted how to ensure a value of CMRR equal to −60 dB in a high frequency field without excessive impact on the value of the occupied silicon area, it may be necessary to completely change the architecture of the sensing circuit 10. In an implementation of the current sensing circuit 20, shown in FIG. 2, some resistances are realized in the High Ohmic Poly Cristalline (HIPO) mode and suitable transconductance elements Gm1 and Gm2 have been introduced.
The sensing circuit 20 comprises the operational amplifier OP, in turn having the first input terminal I1, non-inverting, connected to a first internal circuit node X1 and the second input terminal I2, inverting, connected to the reference terminal TR receiving the reference voltage Vref. Moreover, the sensing circuit 20 comprises a first transconductance element Gm1 having respective input terminals connected to the input terminals IN1 and IN2 of the circuit, and an output terminal connected to the first internal circuit node X1, as well as a second transconductance element Gm2 having a first input terminal connected to a second internal circuit node X2, a second input terminal connected to the reference terminal TR, and an output terminal connected to the first internal circuit node X1. Finally, the sensing circuit 20 comprises a fifth resistance RH1, of the HIPO type, inserted between the reference terminal TR and the second internal circuit node X2, and a second resistance RH2 of the HIPO type inserted between the second internal circuit node X2 and the output terminal Out.
Another embodiment of the approach illustrated in FIG. 2 is shown in FIG. 6, as disclosed in U.S. Pat. No. 6,072,339 to Bertolini, also assigned to the assignee of the present application. In particular, the sensing circuit 30 comprises a so called Gm/Gm stage, substantially realized according to the scheme of FIG. 2, with a feedback that sets the gain to improve the value of CMRR, i.e. the rejection of input common mode.
The sensing circuit 30 comprises a operational amplifier OP having the first inverting input terminal I1 connected to the first internal circuit node X1 and the second input terminal I2, non inverting, connected to a second internal circuit node X2. Moreover, the sensing circuit 30 comprises a first transconductance amplifier A1 having respective input terminals connected to the input terminals IN1 and IN2 of the current sensing circuit 30, and a first and a second output terminal O1, O2 respectively connected to the first circuit node X1 and to the second circuit node X2. The first transconductance amplifier A1 is supplied by a supply voltage Vcc.
In particular, the first transconductance amplifier A1 comprises two transistors T1 and T2 (MOSFET with P channel) that have respective first conduction terminals connected to the supply voltage Vcc through a first biasing resistance R1, respective command terminals connected to the input terminals IN1 and IN2, and respective second conduction terminals which define the output terminals O1 and O2 of the first amplifier A1. Finally, the two transistors T1 and T2 have body terminals connected to each other as well as connected to the positive terminal of the resistance R1.
The sensing circuit 30 comprises a second transconductance amplifier A2. The transconductance amplifier A2 is supplied by the supply voltage Vcc, has a first input terminal in1 connected to a reference terminal TR, receives a reference voltage Vref, and has a second input terminal in2 connected to a third internal circuit node X3. Moreover, the second transconductance amplifier A2 has a first output terminal out1 connected to the first circuit node X1 and a second output terminal out2 connected to the second internal circuit node X2.
In particular, the second transconductance amplifier A2 comprises two transistors T3 and T4 (MOSFET with P channel) that show respective first conduction terminals connected to the supply voltage Vcc through a second biasing resistor R2, command terminals respectively connected to the first in1 and to the second in2 input terminal, as well as respective second conduction terminals, which define the output terminals out1 and out2 of the second amplifier A2. Moreover, the two transistors T3 and T4 have bulk terminals connected to each other as well as to the positive terminal of the resistor R2.
Further, the sensing circuit 30 comprises a first division resistance HIPO RH1 inserted between the reference terminal TR and the third internal circuit node X3, and a second division resistance HIPO RH2 inserted between the third internal circuit node X3 and the output terminal Out. Finally, the sensing circuit 30 comprises a first ground resistor RH3 inserted between the first circuit node X1 and a ground terminal and a second ground resistor RH4 inserted between the second circuit node X2 and the ground terminal Gnd.
According to the present approach, the input terminals IN1 and IN2 of the sensing circuit 30 are connected across a sensing resistor Rs, shown in FIG. 6. The voltage fall on this sensing resistor Rs shows an input differential voltage Vin applied to the input terminals IN1 and IN2 of the sensing circuit 30.
In the present approach, an improved value of CMRR is obtained, i.e. higher, with respect to the value obtained with the use of standard differential amplifiers, for example, the sensing circuit 10 shown in FIG. 1 and described above. This is the result of the presence of the first transconductance amplifier A1 and of the second transconductance amplifier A2.
By using a current sensing circuit in current loop control devices with pulse with input modulation or PWM with typical applications, it may be necessary to ensure a same value of the parameter CMRR for input voltages, which may vary in a range between a null voltage value and a voltage value higher than the supply voltage Vcc. For example, in the case of input voltages varying between −1 V and 14.2 V and a maximum supply voltage Vcc equal to 13.2 V, it may be necessary to ensure a value of the parameter CMRR of at least 70 dB.
In this case, the sensing circuit 30 has some drawbacks. In fact, when the voltages at the input terminals IN1 and IN2 change suddenly, a current flowing in the sense resistor Rs is present, and thus a differential signal is also present, the signal between the maximum value and the minimum value, for example, between 14 V and −1 V, at the input terminals of the two transistors T1 and T2, of the first transconductance amplifier A1. Different voltages are applied, which lead the transistors T1 and T2 to a different biasing state with respect to each other.
In particular, the first transconductance amplifier A1 operates like an open circuit and the two transistors T1, T2 show an inbalance in current. This implies that the signals generated at the output terminals O1, O2 of the first transconductance amplifier A1 propagate in a completely different way with respect to each other in comparison with the transistors T1, T2 being in a balanced state, i.e. they are controlled by voltages present at the input terminals IN1, IN2 that are substantially corresponding.